ISOLDE Project will have high performance RISC-V processing systems and platforms at least at TRL 7 for the vast majority of building blocks, demonstrated for key European application domains such as automotive, space and IoT with the expectation that two years after completion ISOLDE’s high performance components will be used in industrial quality products.
Infineon Technologies AG - Holger Schmidt
Project Duration: 01.05.2023 - 30.04.2026
Email: info
isolde-project [dot] eu
Website: www.isolde-project.eu
LinkedIn: www.linkedin.com/company/isolde-project/
In this page the ISOLDE public deliverable reports are published and available for download. They are structured in-line with the overall ISOLDE structure.
The requirements and specifications will be established early in the project in WP1 and will drive the 3 development WPs. The focus of WP2 is the development of foundational cores including core specific infrastructure IPs as used in the memory hierarchy, such as high-performance caches, NoCs and multi-core support. The focus of WP3 is domain specific accelerators for applications such as cryptography, machine learning and vector units for high-performance. All the work on application SW, tools, compilers and automation will take place in WP4. To ensure that the components will work together and can be used to build systems, multiple demonstrators in 4 domains will be built, and these are the focus of WP5. There are many administrative and legal challenges that are specific to developing complex SoCs that integrate open-source blocks that can have different licensing terms. It is important that these be fully addressed, and these constitute a key aspect of WP6, which also includes the exploitation and dissemination activities. Finally, WP7 covers the project management, including the coordination between partners and reporting to the commission.
Note that only the public deliverables are listed on this page. In case you want more information about a specific deliverable report, please feel free to contact us at infoisolde-project [dot] eu.
OFFIS is developing an open source on-chip co-processor for RISC-V processors to enable high-speed, high-resolution monitoring of timing and behavioral properties on a larger scale than is currently possible. The co-processor allows monitoring of complex application-level processors with full cycle accuracy.
In the design flow of safety-critical applications, the specification of strict timing properties and behavioral guarantees is crucial. One well-known specification method is Contract-Based Design using assume-guarantee contracts. A system model containing such contracts provides a perfect basis for deriving run-time monitor specifications automatically. These specifications are then executed by our newly designed co-processor to achieve continuous monitoring of safety-relevant properties even in large-scale and dynamically evolving applications.
The mentioned contracts supervise various safety requirements covering functional and non-functional properties such as timing, temperature ranges or software parameters. This allows monitoring that a specific controller maintains a parameter within a defined range over a specified time frame, such as running closed-loop motor control parallel to the execution of a specific resource-heavy task, or that a complex AI algorithm always completes its execution within a specified period.
Our contract-based runtime monitoring approach consists of three interacting components:
At its core, the Time Contract Co-Processor (TCCP) connects to two other components, the TCCP-Compiler and the observer interfaces.
The TCCP executes contract-based specifications in hardware, it observes various event sources via an observer interface. The observers are minimalistic adapters to source data, like a RISC-V trace port to observe computational progress or a memory content observer. The TCCP monitors events according to its programmable configuration derived from contract specifications. These specifications are processed by the TCCP compiler, which generates a configuration program for the TCCP. The coprocessor is specifically designed to allow high monitoring capacity and cycle-accurate temporal resolution. Furthermore, enabling updateable contracts via the compiler provides a substantial increase in flexibility over existing statically configured hardware-monitoring approaches.
About OFFIS
OFFIS, an affiliated institute of the Carl von Ossietzky Universität Oldenburg, has been transforming scientific expertise in computer science into innovations since its founding in 1991. These innovations are further developed into marketable products by industrial partners.
The OFFIS production division focuses on the digital transformation of traditional production systems and processes, aiming to achieve various goals. These include improving the efficiency of individual processes or production steps in assembly lines, enabling better cooperation between different machines, enhancing availability through predictive maintenance, and improving quality through error detection during manufacturing.
The ISOLDE consortium recently gathered in Munich on February 11-12, 2025, for a progress project meeting, bringing together partners from across Europe both in person and online. Hosted by HM Hochschule München University of Applied Sciences, this meeting was a proof of the collective expertise, dedication, and collaboration driving ISOLDE forward in its mission to develop high-performance RISC-V processing systems for key sectors such as automotive, space, and IoT.
Over two days of discussions and strategic alignment, the consortium members shared updates on their progress and defined the next steps to accelerate ISOLDE’s objectives. Work package leaders presented significant advancements in areas such as open-source IP core enhancement, system software development, and the integration of accelerators and extensions. Their contributions reflected the commitment and hard work of every member of the consortium involved in the project.
One of the most valuable aspects of the meeting were the workshops, in which partners came together to tackle technical challenges and explore new solutions. These sessions highlighted the strength of ISOLDE’s multidisciplinary approach, leveraging the diverse expertise within the consortium. The open exchange of ideas and knowledge reinforced the strong partnership that is essential for the project's success.
The success of this meeting would not have been possible without the active participation and engagement of all consortium members. A big thank you to everyone who contributed their time, expertise, and enthusiasm—whether attending in person or virtually. The ISOLDE’s consortium dedication is what makes this project a truly collaborative and forward-thinking initiative.
As we continue towards our shared goal of delivering customizable, high-performance IPs hosted on European servers, we look forward to further strengthening our partnerships and achieving new milestones together.
Stay tuned for more updates as ISOLDE continues!
The TRISTAN and ISOLDE projects are working closely together on establishing RISC-V processor technology in Europe. The results of the projects are planned to complement each other. Each project focuses on a different performance class. Both projects’ consortia are composed of partners from industry (both large industries as well as SMEs), research and RISC-V related industry associations.
We are delighted to share the highlights from the latest ISOLDE project meeting, which took place on July 17th and 18th in the city of Bucharest, Romania. This meeting was a key step in the project development as all project partners gathered the appointment either in person or remotely.
During the two-day event, our consortium reviewed the latest updates and advancements within the project. Our discussions focused on the feedback of the previous review meeting in Brussels to refine the technical progress and sharing insights that will drive the ISOLDE project forward. The commitment and dedication of each partner were evident, as all partners collectively navigated through the different challenges that this project proposes.
Additionally, the attendants to this event had the chance to share time with the whole consortium and network to find synergies between all of them.
We are excited about the future of the ISOLDE project and the positive impact it will have in the industry. The productive discussions and renewed energy from this meeting have set a strong foundation for our upcoming phases.
Thank you to all the partners for their active participation and continuous commitment. Stay tuned for more updates as we continue to advance and achieve our project goals.
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads, Matteo Perotti†, Michele Raeber†, Mattia Sinigaglia*, Matheus Cavalcante†, Davide Rossi*, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), ASAP 2024 Conference, https://arxiv.org/abs/2407.05447
Onchip Traffic Injection to Counteract Timing Side-Channel Attacks, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain, Embedded Real Time Systems (ERST) 2024 conference, https://hal.science/hal-04614786
RISC-V on mixed-critical platforms (poster + published extended abstract), Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya and George Violettas, RISC-V Summit Munich 2024,
SETHET – Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story, Gabriele Magnani1, Daniele Cattaneo1, Lev Denisov1, Giuseppe Tagliavini2, Giovanni Agosta1, Stefano Cherubin3; 1 Politecnico di Milano (Italy), 2 University of Bologna (Italy), 3 NTNU (Norway), ACM Computing Frontiers 2024,
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine, Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomas Gomez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini, IEEE Journal of Solid-State Circuits, https://hdl.handle.net/11585/953203
Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching, Matthias Rupp, Stefan Wallentowitz, ARCS Conference 2024,
The European Chips Act, The ISOLDE Project, and Open-Source Hardware, Willibald Krenn; Andrew Wilson; Ambily Suresh; Manuel Freiberger (Silicon Austria Labs, Graz), 2024 Argentine Conference on Electronics (CAE),
MX: Enhancing RISC-V’s Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication, Matteo Perotti†, Yichao Zhang†, Matheus Cavalcante†, Enis Mustafa†, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), DATE 2024 Conference, https://arxiv.org/pdf/2401.04012.pdf
A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation, Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564525
A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems, Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564506
Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, http://hdl.handle.net/2117/397442
SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core, Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella, IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, http://hdl.handle.net/2117/393235
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project, William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario DiCarlo, and Antonio Sciarappa, 1 Politecnico di Milano, Milano, Italy, 2 University of Bologna, Bologna, Italy, 3 E4 Computer Engineering SpA, Italy, 4 Thales Alenia Space Italia S.p.A., Italy, 5 Politecnico di Torino, Torino, Italy, 6 Leonardo SpA, Italy, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2023 conference, https://re.public.polimi.it/retrieve/ceb20d00-33d1-41df-8a37-1870b06ea92...
Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains, Jaume Abella, Francisco J. Cazorla, Sergi Alcaide, Michael Paulitsch, Yang Peng, Inês Pinto Gouveia, (white paper), https://arxiv.org/abs/2307.11940
Last week, the ISOLDE consortium completed its 18-month review to share the latest advancements of the project with the European Commission. The collaboration of all participants provided valuable insights making the session a place for showing the progress of the project and sharing feedback.
This meeting represented a significant milestone for the ISOLDE project, aimed at developing advanced RISC-V processing systems to enhance European industries. Accomplishing this objective holds the potential to revolutionize key sectors in Europe, including automotive, aerospace, and IoT.
During three full days, ISOLDE’s partners dedicated their effort to analyse every element of their work, leaving no doubt about each point of the tasks they needed to discuss and strategizing the path forward.
The attendees at the meeting ranged from our Work Package leaders to some Task leaders and members from all 35 partner organizations, who brought their points of view both in-person in Brussels and remotely.
Moreover, presentations showcased at the event received positive feedback, confirming the dedication of all those involved in the project.
Following the review, the ISOLDE consortium gathered for an after-work social event, providing a welcome opportunity for participants to establish personal connections outside of the professional environment.
The ISOLDE project is growing stronger than ever as its partners continue to attain its goals together. Stay tuned to ISOLDE’s news through our website and social media channels and be aware of all our upcoming milestones!
One of the goals of ISOLDE is to strengthen the dissemination of RISC-V projects in Europe, and ISOLDE partner HM has taken a lead role here with the local organization of RISC-V Summit Europe 2024. It will be held in Munich from June 24 to June 28. As a literal “summit” it will bring together the entire community in Europe, including industry, academia and individual developers.
After the pandemic, there are now three RISC-V Summits around the globe, focusing on the key markets of RISC-V: RISC-V Summit North America, RISC-V Summit Europe and RISC-V Summit China. RISC-V Summit Europe is the joint effort of three key communities from France, Germany and Spain, together with RISC-V International. The steering and program committees include the variety of the European community. Compared to the other summits, Europe traditionally had a more research centric approach, which still reflects on the strong academic impact of the European ecosystem in this community. With over 180 submissions, the RISC-V Summit Europe is the place to present.
But with the rapid adoption of RISC-V in Europe, driven by that strong research ecosystem, we can see an increasing interest and participation from industry. At this year's RISC-V Summit Europe, for example, the CTO of Thales, Bernhard Quendt, will hold a keynote, accompanied by the SVP of Automotive Microcontrollers at Infineon, Thomas Böhm. The key person behind RISC-V, Krste Asanović, will present the State-of-the-Union of RISC-V. Other invited presenters include Alex Kocher, CEO of the Joint Venture Quintauris, and Johanna Bähr, Research Associate at Fraunhofer. Larry Wikelius, Director of the RISC-V Software Ecosystem (RISE) organization will give an update. And last but not least, the first batch of invited speakers includes Edward Wilford of Omdia, who as a Senior Principal Analyst will be speaking about RISC-V adoption in the microcontroller market and beyond.
The program will start on Monday with Technical Workgroup Meetings. The main program and expo will run from Tuesday to Thursday. Friday will be available for RISC-V focused projects to meet or disseminate their work. As RISC-V Summit Europe is the denoted “main summit” this year, the annual general meeting of all RISC-V members and an award ceremony will be part of the program.
About the HM:
Hochschule München (HM) is one of the largest universities of applied sciences in Germany. Their technical involvement in ISOLDE focuses on open-source CPU support for bytecode virtualization and an improved fault injection framework around the open-source tool Verilator. Beyond the technical contributions, HM is strongly involved in dissemination events. With HM professor Stefan Wallentowitz on the RISC-V board of directors, an impactful advocate of RISC-V is active in the ISOLDE project.
The overarching aim of ISOLDE is to provide a high-performance RISC-V based system-on-a-chip (SoC) with a level of functionality, safety, security and power efficiency that is competitive with existing commercial/proprietary alternatives.
At the FZI, we support this vision with an approach to integrate safety patterns for hardware using a model-driven design approach. The foundation builds the Rocket Chip Generator framework maintained by the Chips Alliance. Using a model-driven approach, the architecture of the hardware design is abstracted and transformations on this abstract model integrate different architectural safety patterns, such as Triple Modular Redundancy (TMR). By feeding back the modified model into the generator approach, the hardened architecture can be generated and afterward synthesized.
For the model-driven approach, we build upon the Universal Safety Format (USF), which was primarily designed for hardening software architectures. Within ISOLDE, we would like to adopt this format and the underlying principles for hardware designs. By choosing an approach originating form software, we anticipate creating a design flow that can address both the hardware as well as the corresponding software part that is often required when introducing hardware safety features, such as a watchdog timer.
This automated integration approach is supported by an early system-level/RTL co-simulation approach. We utilize the design artifacts of the Rocket Chip Generator, such as the RTL description of the peripherals as well as the device tree of the SoC, to generate simulation models and configure a QEMU core simulation. With such a simulation, it is possible to evaluate the hardware/software system, especially the effectiveness of the integrated safety mechanism.
The two approaches enable a rapid exploration of different safety architectures in the generative SoC design flow.
About the FZI:
As an independent foundation, the FZI Research Center for Information Technology has stood for applied cutting-edge research in the field of computer science and its application fields for over 35 years. The FZI researches and develops innovations for the benefit of society and offers excellent researchers a unique springboard to their professional future. For its partners from industry, business, science, associations, and the public sector, the FZI serves as an institution research, training and transfer.
Research teams at the FZI interdisciplinarily develop and prototype concepts, software, hardware and system solutions for their clients. Scientific excellence and interdisciplinary practice are therefore well established at the FZI.
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