ISOLDE Project will have high performance RISC-V processing systems and platforms at least at TRL 7 for the vast majority of building blocks, demonstrated for key European application domains such as automotive, space and IoT with the expectation that two years after completion ISOLDE’s high performance components will be used in industrial quality products.
Infineon Technologies AG - Holger Schmidt
Project Duration: 01.05.2023 - 30.04.2026
Email: info
isolde-project [dot] eu
Website: https://www.isolde-project.eu
LinkedIn: https://www.linkedin.com/company/isolde-project/
Virtual Repository: https://www.isolde-project.eu/virtual-repository
The ISOLDE project, funded by the Key Digital Technologies Joint Undertaking (KDT JU), aims to develop European high-performance RISC-V-based CPUs, achieving functional and non-functional improvements to compete with proprietary alternatives or surpass them. Project partners from leading EU universities and companies will develop advanced architectures, novel accelerators, and reusable IPs, forming a robust compute infrastructure for applications in automotive, industrial, and aerospace domains. The ISOLDE project seeks to establish an European sovereignty in semiconductors, closing the confidence gap, and driving adoption through prototype solutions, documentation, and benchmarks.
Within this project, a demonstrator is developed targeting the space use-case, to showcase the IPs developed in ISOLDE and aiming at revolutionizing onboard computational capabilities for space applications by leveraging RISCV cores and accelerators, integrated with an advanced software layer, to create a hardware and software platform capable of meeting the dual challenges of demanding computing and memory requirements and the harsh environmental constraints of space.
A key innovation of the project is to harness the CVA6 processor family and tensor accelerators, all connected through the open standard BUS protocol AXI4, to enable processing capabilities closer to the sensor and support the development of onboard inference capabilities. Compute intensive applications are offloaded to dedicated accelerators controlled by the Cheshire system host and can communicate directly with the memory through dedicated DMAs, relieving the host from unnecessary CPU cycles. This approach aims to transform traditional workflows, where satellite data, such as Earth observation images, undergo initial preprocessing onboard before being transmitted to ground stations for high performance computing. By bringing these processing steps onboard, the project not only minimizes uplink and downlink requirements, but also accelerates real-time decision-making and enhances satellite autonomy.
The space demonstrator targets a low-Earth orbit satellite use-case, inspired by the Sentinel-2 mission, and encompasses a broad range of applications, such as Earth observation, avionic functionalities and attitude orbit control (AOC), and telemetry processing for fault detection, identification, and recovery (FDIR). Beyond these traditional domains, the ISOLDE space demonstrator focuses on artificial intelligence (AI) models to further enhance spacecraft autonomy. These models will be crucial for applications such as wildfire detection from hyperspectral images captured by the multi-spectral instrument (MSI) and FDIR using telemetry data from the Attitude Control System (ACS). The performance of these AI algorithms will be evaluated on the new hardware, showcasing their potential to redefine the role of onboard computing in space systems.
About Leonardo
Leonardo is a global industrial group that creates multi-domain technological capabilities in the Aerospace, Defence and Security sector. With over 60,000 employees worldwide, the company has a significant industrial presence in Italy, the UK, Poland and the US. It also operates in 150 countries through subsidiaries, joint ventures and investments. A key player in major international strategic programmes, it is a technological and industrial partner of governments, defence administrations, institutions and companies. In 2024, Leonardo recorded consolidated revenues of €17.8bn, new orders for €20.9bn and invested €2.5bn in R&D. Innovation, continuous research, digital industry and sustainability are the pillars of its business worldwide.
In the context of the ISOLDE project, Politecnico di Milano (PoliMi) develops approximate computing technologies at the hardware and software level, cryptographic accelerators, and efficiency enhancements for real-time computing. The proposed advances are applied to the Space demonstrator RISC-V-based platform.
Approximate Computing is an emerging paradigm that attempts to improve the energy efficiency of computation, a critical issue for battery-powered embedded systems as well as to address the increasing energy footprint of ICT worldwide, by trading off some of the computation accuracy.
Briefly, in any computer system, all computations are performed with a certain degree of accuracy, i.e., on a fixed number of digits (more precisely, of bits). This number of digits is usually vastly oversized with respect to the actual ranges of the numeric values computed, to minimize the risk of errors.
The TAFFO framework enables the reduction of the data size, as well as the switching between different types of data representations (e.g., floating point, fixed point, etc.) to trade off accuracy that is not actually needed by the computation for lower energy consumption, obtained by employing custom hardware, such as the customized floating point unit also developed by PoliMi, or by adapting to the available hardware characteristics (e.g., switching to fixed point when a hardware floating point unit is not available at all).
With the seTHet and luTHet extensions developed in ISOLDE, TAFFO is also able to efficiently exploit the memory subsystem of an heterogeneous system, by tuning the precision in accordance to the available direct memory access bandwidth and by tabulating costly trigonometric functions instead of computing them.
Considering a Sobel edge detection, a different tuning of the available memory for trigonometric function tabulation minimally affects the quality of the output yielding a 30× speedup and, consequently, a reduction of the total energy by the same factor. The framework then selects the best solution according to the required quality and the available memory.
Politecnico di Milano is the foremost technical university in Italy, with over 45,000 students in engineering, architecture and design, and is ranked among the first in the European Union according to the 2025 QS ranking. The university also serves as a technology development and transfer hub, with over 100 spin off companies and over 3000 patents. Within Horizon Europe, it has obtained funding for over 150M€ in over 300 projects, including 36 ERC grants.
The HEAP laboratory of the Department of Electronics, Informatics and Bioengineering is a cross-disciplinary research team of around 20 people with skills covering Embedded and Cyber Physical Systems, Design Methodologies, Low-power Design of Software and Hardware, Compiler Construction, and Embedded Systems Security and Data Privacy.
The group has been active for over two decades in designing architectures and in developing methodologies and prototype tools to support the automation of different design phases of advanced embedded and computing systems.
The summer period has been an important time for the ISOLDE project, marked by key milestones and fruitful exchanges across Europe.
In early July, representatives of our Work Package Leaders attended the official project review meeting in Brussels. This review was a significant moment to reflect on the progress made so far, showcase the results achieved, and receive constructive feedback from the EC reviewers. We are proud to share that the outcome was very positive, confirming that ISOLDE is on the right track to deliver on its ambitious objectives. The reviewers also provided valuable recommendations, which will help us shape our next steps with even greater precision and impact.
Later in the month, members of the consortium came together in Munich for an in-person meeting. This gathering offered the perfect setting to discuss in detail the future work plan, align our strategies with the recommendations from the review, and strengthen our collaborative spirit. The agenda combined technical discussions with opportunities for open exchange, fostering both focused work and creative thinking.
Our time in Munich was not only about work — we also took the chance to organise a social programme, allowing team members to connect beyond the meeting room. These moments of informal interaction help reinforce the trust, understanding, and shared commitment that underpin the success of the project.
An additional highlight of the Munich meeting was a joint workshop with four sister projects: TRISTAN, REBECCA, RIGOLETTO, and Scale4Edge. This collaborative session was designed to learn more about each project’s goals, approaches, and progress, while identifying potential synergies and areas for alliance. Such cross-project exchanges are essential for building a strong research and innovation ecosystem, ensuring that efforts complement rather than duplicate each other, and opening the door to new opportunities for cooperation.
The combination of a successful project review, a productive consortium meeting, and a great workshop with related initiatives made July a month of momentum for ISOLDE. With renewed energy and clear direction, we look forward to implementing the next phase of our work.
The gap between design and implementation is a bottleneck in hardware development. With Register-Transfer Level (RTL) generation often neglecting the physical implementation constraints tapeouts can delayed or even broken. As RTL-models – sometimes already called RTL-programs – are said to be the way for technology independent digital designs this challenge is often despised. Even more, re-use of RTL-IPs is claimed to be the way to close the digital design gap, that is the disparity between the growth of manufacturable transistors and the ability to design circuits and systems that effectively utilize them.
However, as the physical reality is ignored the re-use rate is lower than planned. When digging deeper, following four major reasons can be identified. First, different features and feature variants of an IP are needed to fully cover the potential of re-use and to avoid modifications in code that is claimed to be re-usable. Examples include the number of channels in communication-IPs or timer-IPs, the sizes of objects used for holding addresses or data, or slight variations in implementation. Second, the soft-IP must operate in different domains and under different conditions. Therefore, it is required to provide special features, e.g., safety, security, or (self-) test features. Third, even though RTL code can conceptually be synthesized to any semiconductor target technology, some code items in the RTL code such as instantiating clock gates, memories, or pads remain technology-specific. Further, meeting timing constraints may partially require to implement functionalities differently. Last but not least – and fourth - FPGA prototypes are increasingly used for validation purposes, making it essential to ensure the seamless mapping of RTL code to both ASIC and FPGA technologies.
All these challenges require the RTL code to follow different and sometimes partially contradicting requirements. One approach to tackle these challenges is making use of so-called generic IPs that can be configured with generics (VHDL) or parameters (SystemVerilog). However, generic-IPs can support different object sizes but do not provide features like optional ports or flexibility in instantiating components. To enhance adaptability, generator-based approaches have been developed that leverage partly hardware generation languages (HGL). VHDL and SystemVerilog configurations conceptually can (re-)configure component instantiations but this feature is not supported by synthesis tools.
As the HDL and HGL approaches cover the mentioned challenges only to some extent the Model-Driven Architecture (MDA)-based code generation, an iterative flow of model refinements and final un-parsing, is the way of choice to generate RTL and other collaterals in a highly reusable way. With the MDA inherent transformation and generator approach, RTL code can be provided in a significantly more flexible manner, supporting facets such as feature dependent ports or port properties. In addition, MDA promotes the idea of creating abstract models that describe system functionality, which can then be automatically or semi-automatically transformed into RTL code. This approach is appealing due to its promises of efficiency, reusability, and reduced human error. From a high-level perspective, re-use of code is replaced by re-using transformation and generation utilities.
The picture on the left gives an overview on the process. Generation that starts with a Computation Independent Model (CIM). We call this model Model of Things (MoT) as only things, their attributes and relations are defined. This model is translated in a Platform Independent (Implementation) Model, which we call Model of Design (MoD) as it includes already most of the design aspects. With a transformation, the MoD is migrated to a MoD’ which is still platform independent put easier to translate to the target platform. The target platform specific code is finally reached by translating to a Platform Specific Model (PSM), which we call Model of View as it closely relates to the target formalism. The MoV is finally unparsed to the target code. As hardware platforms are inherently heterogeneous and often optimized for specific use cases, platform awareness is an essential requirement for getting the best results. For example, the priority for a CPU-centric SoC would be high clock speeds and general-purpose processing. For FPGA platforms, however, parallelism and reconfigurability are keys. Defining and considering metrics such as timing constraints, resource availability, and power considerations, highly influence the power, performance, and area (PPA) attributes of a design.
PAF, the Platform Aware Flow, is a systematic platform-model (PM)-based approach aimed at unlocking the full potential of MDA based RTL generation by enhancing the platform awareness while preserving the abstraction advantages. The approach leverages a Platform Model (PM) to improve the overall chip design flow by enabling the generation of platform-aware RTL, along with platform-specific constraints and directives whilst keeping the generator well structured. These enhancements guide backend tools to achieve better quality results, facilitate faster design closure, and incorporate testing and safety features tailored to the target platform. This approach bridges the gap between RTL and implementation through increasing automation. It also ensures that the resulting chips meet testability and safety requirements.
A sketch of a Platform Model is shown on the left. It is composed of aspect specific sub-models besides platform descriptive attributes. These sub-models steer the PIM-to-PIM’ and PIM’-to-PSM transformations. Each of that covers other aspects as timing and power, technology specific components or safety specific properties.
The key to the PAF-approach is to introduce platform models as conceptually foreseen by the MDA vision. Second pillar is a flexible engine that interprets platform models and modifies design models through a set of fundamental editing operations, resulting in RTL code that is tailored for the target platform. We further utilize the platform models together with the design model to generate other collaterals. We have demonstrated the effectiveness of our approach through qualitative analysis and quantitative results, ultimately showing a significant 73% reduction in code generation effort for industrial-grade designs. By bridging the gap between design and implementation, our Platform-Aware RTL Generation flow has the potential to revolutionize the hardware development process as well as enabling faster time-to-market, improved design quality, and reduced development costs.
Watch now the lightning talk by Florian Wohlrab regarding the Contribution towards European sovereignty for embedded processors in ISOLDE and TRISTAN at RISC-V Summit Europe 2025.
In the ISOLDE Project, IMT contributes to both algorithm development and digital designs. We are adapting split-radix algorithms for hardware acceleration of the Fast Fourier Transform (FFT) used in signal processing and high-performance computing, as well as for Number Theoretic Transforms (NTT) applied in post-quantum cryptography. Additionally, we are designing a SIMD/Vector accelerator optimized for matrix operations and a high-bandwidth, multi-port scratchpad memory.
At IMT, we utilize FFT for specially designed coded sequences in acoustic sensors, enabling longer acquisition times to achieve a better signal-to-noise ratio. A hardware-accelerated FFT will allow IMT to dynamically adapt these coded sequences to time-varying environmental conditions. Additionally, we employ FFT to solve partial differential equations on periodic cells, facilitating the estimation of macroscopic properties from 2D/3D images of microstructures. These applications span a broad range of physical phenomena, including two-phase flow prediction in porous media, the dielectric behavior of biological cells, and anisotropic crystal plasticity in metals and metallic alloys. This creates opportunities for real-time integration of micro-macro predictions into quality assessment and control systems.
Separately, we investigate algorithms for the Number Theoretic Transform (NTT), the counterpart of the FFT for integer arithmetic in finite fields, with applications in fast polynomial multiplication within finite polynomial rings. This operation is among the most computationally and energy-intensive tasks in Post-Quantum Cryptography (PQC) based on Ring/Module Learning With Errors. A challenge is that only a limited selection of finite rings supports NTT. While some PQC algorithms are specifically designed around NTT-friendly choices, others deliberately avoid them to reduce the attack surface. Our work focuses on developing universal NTT algorithms, leveraging complex transforms for generalized Mersenne primes and real transforms for powers of Fermat primes.
IMT also contributes to the development of a SIMD/Vector accelerator, a tightly coupled hardware extension for RISC-V cores. This accelerator features software-defined two-dimensional registers and enhances matrix operations, which are widely used in Artificial Intelligence (AI), particularly in Machine Learning (ML). It is integrated with the main core via the RISC-V extension interface, specifically the new CoreV-eXtension-Interface (CV-X-IF).
The proposed accelerator has two interfaces: one connecting to the main core and another to the main memory which is also used at unloading memory operations from the core. The new CV-X-IF interface for RISC-V cores enables the extension of the Instruction Set Architecture (ISA) with new opcodes and provides direct access to core registers, significantly simplifying the design of tightly coupled accelerators. Figure 1 illustrates the accelerator’s role in the system and its interactions with other components.
Figure 1. SIMD/Vector accelerator: Interfaces and internal organization
The National Institute for R&D in Microtechnologies IMT-Bucharest (Romania) is a non-budgetary public research unit. The main research fields are in closed connection to four Key Enabling Technologies: micro-nanoelectronics, photonics, nanotechnology and advanced materials.
The research centers that compose IMT are MIMOMEMS : European Research Centre of Excellence (Micro- and nano-systems for radiofrequency and photonics), CNT-IMT: Center of Nanotechnologies, CINTECH: Research Centre for integration of technologies (micro-nano-biotechnologies) and CENEASIC: Research Centers for nanotechnologies devoted to advanced carbon based integrated nanosystems and nanomaterials. The latter is also one of the fabrication facilities inside IMT, alongside MINAFAB: Center for Micro and NAnoFABrication.
The laboratories inside the institute that drive innovation across various fields include microsystems for biomedical and environmental applications, nanobiotechnology, molecular nanotechnology, micro-nano photonics, micromachined structures, microwave circuits and devices, as well as simulation, modeling, and reliability. With a team of 200 experts in electronics, computer science, physics, chemistry, and biology, IMT has participated in over 100 European projects (Horizon Europe, H2020, FP7, FP6, bilateral cooperation). As a result, it has become a recognized partner in numerous multidisciplinary consortia and networks.
In this page the ISOLDE public deliverable reports are published and available for download. They are structured in-line with the overall ISOLDE structure.
The requirements and specifications will be established early in the project in WP1 and will drive the 3 development WPs. The focus of WP2 is the development of foundational cores including core specific infrastructure IPs as used in the memory hierarchy, such as high-performance caches, NoCs and multi-core support. The focus of WP3 is domain specific accelerators for applications such as cryptography, machine learning and vector units for high-performance. All the work on application SW, tools, compilers and automation will take place in WP4. To ensure that the components will work together and can be used to build systems, multiple demonstrators in 4 domains will be built, and these are the focus of WP5. There are many administrative and legal challenges that are specific to developing complex SoCs that integrate open-source blocks that can have different licensing terms. It is important that these be fully addressed, and these constitute a key aspect of WP6, which also includes the exploitation and dissemination activities. Finally, WP7 covers the project management, including the coordination between partners and reporting to the commission.
Note that only the public deliverables are listed on this page. Only public deliverables approved by the Chips JU can be downloaded from this page. If you would like more information about a specific deliverable report, please feel free to contact us at infoisolde-project [dot] eu.
30 November 2023
The purpose of this document is to collect the initial requirements for the demonstrators in the chosen application areas (Automotive, Space, Smart home, IoT), as worked out in T1.1.
It contains both functional and non-functional requirements, at least from the following subjects: architecture (components, interfaces, accelerators), measurable metrics and goals (performances, power consumption, radiation tolerance, security metrics to be used), SW requirements (stacks, tools, system SW features, SW for demonstrators use cases), and standard to be used/considered.
The main goal of this document is to have a sound starting basis for further iteration and refinement in the different WPs of the project. Some of the requirements have already been worked out in full detail, while others still contain some open questions or issues to be finalized. For example, regarding verification and validation, further refinement and updates are still needed. Such activity will be carried out in D1.3 where the final requirements will be frozen.
This document supports the technical report associated to the deliverable D1.1 "Demonstrators Requirements and Specifications" reporting to the WP1 "Requirements and Specifications" leader (E4 Computer Engineering S.p.A.) for the Project ISOLDE.
The document is prepared in the frame of the Task 1.1 – Collection of requirements of the demonstrators & high-level SoCs specifications (WP1).
30 November 2023
This Deliverable reports an initial list of requirements and specifications for the various components developed in the context of the ISOLDE project relative to core architecture, hardware and software modules. In addition, this Deliverable provides a first indication about the IP corresponding to each component. A consolidated version of this document will be produced as a follow-up Deliverable D1.4. All partners involved in Tasks 1.2, 1.3 and 1.4 contributed to this Deliverable.
21 May 2024
The purpose of this document is to collect the requirements for the project demonstrators in the chosen application areas (Automotive, Space, Smart home, IoT), as worked on in T1.1 "Collection of requirements of the demonstrators & high-level SoCs specifications" (M1-M12). The base for this document is the information contained in D1.1 "Demonstrators requirements and specifications", and D1.2 "Requirements and specifications on architecture, hardware and software modules and IPs", which has been updated following the progress of the work done in WP2, WP3, WP4 and WP5 adding also more detail on IPs implementation as well as the definitions of the architectures of the planned demonstrators. D1.3 is the final outcome of T1.1.
The document contains both functional and non-functional requirements for the following subjects: architecture (components, interfaces, accelerators), measurable metrics and goals (performances, power consumption, radiation tolerance, security metrics to be used), SW (stacks, tools, system SW features, SW for demonstrators use cases). There are also references, where significant, to standard to be used/considered.
D1.3 includes an overview of each demonstrator, whose objectives and proposed architecture are described in more detail in D5.1 "Description of demonstrators architecture" (due M12, same as this document), to contextualize the requirements and the verification strategy attached to them.
This document supports the technical report associated to the deliverable D1.1 "Demonstrators Requirements and Specifications" reporting to the WP1 "Requirements and Specifications" leader (E4 Computer Engineering S.p.A.) for the Project ISOLDE.
27 January 2025
This document describes the work performed within ISOLDE WP2 Open-Source Foundation Cores. WP2 will develop IPs that will be delivered through internal repositories during the work and finally through the ISOLDE virtual repository. WP2 progress will be reported through updates of this report that will be issued as document deliverables D2.2 (M18) and D2.3 (M33).
The requirements and specifications for the work to be performed is established in WP1. At the time of issuing this report, much of the work to be carried out in WP2 is still in the specification or planning stage.
13 November 2024
This document describes the work performed within ISOLDE WP2 Open-Source Foundation Cores. It is the update of document deliverable D2.1 (M6). WP2 is developing IPs that will be delivered through internal repositories during the work and finally through the ISOLDE virtual repository. WP2 progress will be reported through update of this report that will be issued as document deliverable D2.3 (M33).
The requirements and specifications for the work to be performed is established in WP1. At the time of issuing this report, much of the work to be carried out in WP2 is now in the implementation stage.
21 May 2024
The ISOLDE project aims to create high-performance processing systems and platforms targeting different use cases (space, automotive, smart home, cellular IoT) based on the free, open-source RISC-V instruction set architecture. This document defines the initial architecture of the required hardware modules and extensions (called extensions in the following) developed within the work package WP3 "Accelerators and Extensions" of the ISOLDE project to reach this goal. It encompasses contributions from all tasks (T3.1 to T3.6) and partners within WP3.
The extensions described in this report are grouped into different domains matching the scope of the different tasks within WP3:
For each extension, this document contains general information (type, dependencies, and license) and an initial architecture description giving a first insight into its purpose and internals. These initial architecture descriptions answer core questions about each extension:
WP5 "Use Cases and Demonstrators" will combine the foundational cores developed by WP2 "Open-source Foundation Cores" and selected features from WP3, building diverse demonstrators (space, automotive, smart home, cellular IoT) that highlight benefits and opportunities enabled by individual extensions. Further, WP4 "System Software, Development Tools and Automation" will provide the required software support (e.g., toolchains, operating system support, drivers). Hence, the contributions of this deliverable are crucial for further collaboration with these work packages. In the context of WP3, this deliverable is the basis for the follow-up deliverables covering the prototype and final implementations of the extensions (D3.2, D3.3 in M24 and D3.4, D3.5 in M33). The components described in this deliverable are aiming at different maturity levels and aiming for different certifiability. Further, this document represents the first iteration of the architecture definitions and hence not all contributions have the same level of maturity. A short survey of the ISOLDE partners for certification intentions (including WP3 components) will be later provided by SYSGO as part of WP1 work.
29 April 2025
The ISOLDE project aims to create high-performance processing systems and platforms targeting
different use cases (space, automotive, smart home, cellular IoT) based on the free, open-source
RISC-V instruction set architecture.
This documents refine the architecture and describe the prototype implementations of the hardware
modules related to safety and security, previously introduced in Deliverable D3.1. These
modules have been developed within the work package WP3 "Accelerators and Extensions" of
the ISOLDE project, more particularly in tasks T3.1 and T3.3.
The extensions described in this report are grouped into different domains matching the scope of
some different tasks from WP3:
For each safety / security extension, this document contains refined architecture description since
deliverable D3.1, reminding the purpose of the extension, where in the system is it integrated,
and which other systems it is connected to. We then provide a more detailed description on
the hardware module internals, describing the prototype that allow the hardware module to be
evaluated / verified.
WP5 "Use Cases and Demonstrators" will combine the foundational cores developed by WP2
"Open-source Foundation Cores" and selected features from WP3, building diverse demonstrators
(space, automotive, smart home, cellular IoT) that highlight benefits and opportunities enabled by
individual extensions. Further, WP4 "System Software, Development Tools and Automation" is
providing the required software support (e.g., toolchains, operating system support, drivers).
Hence, the contributions of this deliverable are crucial for further collaboration with these work
packages. In the context of WP3, this deliverable is the basis for the follow-up deliverable covering
the final implementations of the extensions (D3.4, D3.5 in M33). The components described in
this deliverable are aiming at different maturity levels and aiming for different certifiability.
30 April 2025
Deliverable D3.3 presents the prototype implementations of hardware accelerators developed
within Work Package 3 (WP3) of the ISOLDE project. These components target key computational
domains—including AI/ML, cryptography, signal processing, and virtualization—supporting
the project’s goal of building customizable and efficient RISC-V-based platforms for embedded
applications.
The deliverable includes over 20 synthesizable and evaluable IPs, organized across the following
categories:
Each IP is described via a standard template ("IP Card") detailing functionality, architecture, integration
interface, maturity level, and evaluation results (e.g., FPGA/ASIC synthesis, performance,
power).
This deliverable represents a transition from design to validated prototype, supporting downstream
integration with WP5. It forms the technical baseline for final implementation deliverables D3.4
and D3.5.
13 May 2024
This Deliverable reports the proposed architectures of the four Demonstrators (Space, Automotive, Smart Home, Cellular IoT) in four separate sections, as well as providing a more detailed description of the use case applications. A consolidated version of the Demonstrator requirements is instead provided in Deliverable D1.3, written at the same time. All partners involved in WP5 contributed to this Deliverable.
22 May 2024
This document is prepared in the frame of the Tasks 6.2 "Outreach and Dissemination" and Task 6.3 "Exploitation" – (WP6).
Since ISOLDE is an open-source project, dissemination is essential for many reasons. Firstly, for maximizing impact: open-source projects thrive on collaboration and community engagement. Dissemination allows project outcomes and innovations to reach a wider audience, increasing the potential for adoption and utilization. By sharing knowledge, code, and documentation, open-source projects can have a broader impact and contribute to solving real-world problems. ISOLDE is aimed to build and contribute to the Reduced Instruction Set Computing (RISC)-V ecosystem in Europe, and although we have many stakeholders available in the project, outreach to external stakeholders is essential to reach maximum impact. This will also be done in close cooperation with the TRISTAN project which has similar ambitions. ISOLDE differentiates from TRISTAN by focusing on "stronger" application processors as to the "smaller" processors targeted by TRISTAN.
A well-designed dissemination approach will facilitate new collaborations. By making ISOLDE results publicly available, it becomes easier for others to contribute, provide feedback, and build upon the work done. This collaborative approach fosters innovation and accelerates the development of new ideas and solutions. Extension of the ISOLDE network to other stakeholders in open-source will help to increase the community and that will foster acceleration of innovations within ISOLDE.
Finally, we strongly believe that by getting feedbacks during dissemination activities from the RISC-V community, the quality and reliability of the IP blocks developed in ISOLDE will be improved. Although ISOLDE targets to achieve a Technology Readiness Level (TRL) 6, a large stakeholder community can help identify bugs, improve functionality, and enhance the overall quality and reliability of the project. This deliverable describes through the proposed dissemination plan the methodology and tools to be used to generate maximum dissemination impact.
Beyond dissemination, exploitation is also of crucial importance. Exploitation is a must-have to ensure that results end up in the market in a successful way. ISOLDE primarily aims to enhance and mature the European RISC-V ecosystem and to support the ongoing shift towards open source methodologies and solutions in that context. Therefore, one of the results will be exploited via open-source and others via different licensing mechanisms. Some of the results will remain company-confidential and will be exploited by individual partners on the market. This first version of the exploitation plan has been drafted at the end of year 1 of ISOLDE. During this stage initial technical results have been achieved, but technical maturity still needs to increase. The information in Section 3 of this document supplements exploitation information in Part A and Part B of the Grant Agreement and includes contributions from partners with addenda thereto.
28 May 2024
This document describes the work performed within ISOLDE WP6 – Open – source Strategy, Business Models, Exploitation and Dissemination in Task 6.1.
A consolidated version of this Deliverable provides info and can demonstrate that networking within the realm of RISC-V, open-source technology, embedded processor development, and SoC application design can greatly expand ISOLDE reach and impact.
25 November 2024
This document describes the work performed within ISOLDE’s Task 6.2: Outreach and dissemination from WP6 and continues the legacy of deliverable D6.1: Initial Plan on Dissemination & Exploitation.
This document outlines a well-defined and customized ISOLDE dissemination and communication plan, highlighting the use of the different dissemination tools, strategies, and planned activities as of October 2024 used by the consortium. These include not only individual work performed by partners, but also joint actions. To achieve this, the dissemination strategy aims to raise awareness and interest in the solution developed during the project among the different audiences.
Since ISOLDE is an open-source project, dissemination is essential for many reasons. Firstly, for maximizing impact: Open-source projects thrive on collaboration and community engagement. Dissemination allows project outcomes and innovations to reach a wider audience, increasing the potential for adoption and utilization. By sharing knowledge, code, and documentation, open-source projects can have a broader impact and contribute to solving real-world problems. ISOLDE is aimed to build and contribute to the RISC-V ecosystem in Europe, and although the consortium has many stakeholders available in the project, outreach to external stakeholders is essential to reach maximum impact. This will also be done in close cooperation with the TRISTAN project, which has similar ambitions.
A well-designed dissemination approach will facilitate new collaborations. By making ISOLDE results publicly available, it becomes easier for others to contribute, provide feedback, and build upon the work. This collaborative approach fosters innovation and accelerates the development of new ideas and solutions. Extension of the ISOLDE network to other stakeholders in Open Source will help to increase the community and that will foster acceleration of innovations within ISOLDE.
Finally, the consortium strongly believes that by increasing the RISC-V community through dissemination, it will strongly contribute to the quality and reliability of the IP blocks developed in ISOLDE. Although TRL6 is foreseen as endpoint, a large stakeholder community can help identify bugs, improve functionality, and enhance the overall quality and reliability of the project. This dissemination plan will describe the methodology and tools to be used to generate maximum dissemination impact.
30 April 2025
The ISOLDE project aims to significantly address the RISC-V growing demand: by the end of our project, we will have high-performance RISC-V processing systems and platforms at least at Technology Readiness Level (TRL) 7 for the vast majority of the proposed architecture components, with the expectation that 2 years after project completion, ISOLDE’s high-performance components will be used in industrial quality products. Moreover, the project extends its expertise to the realm of computing by spearheading the development of multi-precision Vector processing units integrated with RISC-V cores. This initiative seeks to enhance computing efficiency for specific applications while furnishing Europe and the open-source community with innovative solutions to computational challenges.
This document describes the virtual repositories of ISOLDE IP as a summarizing work performed within ISOLDE WP6 – Open – source Strategy, Business Models, Exploitation and Dissemination in Task 6.1. A consolidated version of this Deliverable provides information and can demonstrate that networking within the realm of RISC-V, open-source technology, embedded processor development, and SoC application design can greatly expand ISOLDE reach and impact.
OFFIS is developing an open source on-chip co-processor for RISC-V processors to enable high-speed, high-resolution monitoring of timing and behavioral properties on a larger scale than is currently possible. The co-processor allows monitoring of complex application-level processors with full cycle accuracy.
In the design flow of safety-critical applications, the specification of strict timing properties and behavioral guarantees is crucial. One well-known specification method is Contract-Based Design using assume-guarantee contracts. A system model containing such contracts provides a perfect basis for deriving run-time monitor specifications automatically. These specifications are then executed by our newly designed co-processor to achieve continuous monitoring of safety-relevant properties even in large-scale and dynamically evolving applications.
The mentioned contracts supervise various safety requirements covering functional and non-functional properties such as timing, temperature ranges or software parameters. This allows monitoring that a specific controller maintains a parameter within a defined range over a specified time frame, such as running closed-loop motor control parallel to the execution of a specific resource-heavy task, or that a complex AI algorithm always completes its execution within a specified period.
Our contract-based runtime monitoring approach consists of three interacting components:
At its core, the Time Contract Co-Processor (TCCP) connects to two other components, the TCCP-Compiler and the observer interfaces.
The TCCP executes contract-based specifications in hardware, it observes various event sources via an observer interface. The observers are minimalistic adapters to source data, like a RISC-V trace port to observe computational progress or a memory content observer. The TCCP monitors events according to its programmable configuration derived from contract specifications. These specifications are processed by the TCCP compiler, which generates a configuration program for the TCCP. The coprocessor is specifically designed to allow high monitoring capacity and cycle-accurate temporal resolution. Furthermore, enabling updateable contracts via the compiler provides a substantial increase in flexibility over existing statically configured hardware-monitoring approaches.
About OFFIS
OFFIS, an affiliated institute of the Carl von Ossietzky Universität Oldenburg, has been transforming scientific expertise in computer science into innovations since its founding in 1991. These innovations are further developed into marketable products by industrial partners.
The OFFIS production division focuses on the digital transformation of traditional production systems and processes, aiming to achieve various goals. These include improving the efficiency of individual processes or production steps in assembly lines, enabling better cooperation between different machines, enhancing availability through predictive maintenance, and improving quality through error detection during manufacturing.
The ISOLDE consortium recently gathered in Munich on February 11-12, 2025, for a progress project meeting, bringing together partners from across Europe both in person and online. Hosted by HM Hochschule München University of Applied Sciences, this meeting was a proof of the collective expertise, dedication, and collaboration driving ISOLDE forward in its mission to develop high-performance RISC-V processing systems for key sectors such as automotive, space, and IoT.
Over two days of discussions and strategic alignment, the consortium members shared updates on their progress and defined the next steps to accelerate ISOLDE’s objectives. Work package leaders presented significant advancements in areas such as open-source IP core enhancement, system software development, and the integration of accelerators and extensions. Their contributions reflected the commitment and hard work of every member of the consortium involved in the project.
One of the most valuable aspects of the meeting were the workshops, in which partners came together to tackle technical challenges and explore new solutions. These sessions highlighted the strength of ISOLDE’s multidisciplinary approach, leveraging the diverse expertise within the consortium. The open exchange of ideas and knowledge reinforced the strong partnership that is essential for the project's success.
The success of this meeting would not have been possible without the active participation and engagement of all consortium members. A big thank you to everyone who contributed their time, expertise, and enthusiasm—whether attending in person or virtually. The ISOLDE’s consortium dedication is what makes this project a truly collaborative and forward-thinking initiative.
As we continue towards our shared goal of delivering customizable, high-performance IPs hosted on European servers, we look forward to further strengthening our partnerships and achieving new milestones together.
Stay tuned for more updates as ISOLDE continues!
