Synergistic memory optimisations: precision tuning in heterogeneous memory hierarchies, Gabriele Magnani 1, Daniele Cattaneo 1, Lev Denisov 1, Giuseppe Tagliavini 1, Giovanni Agosta 1, Stefano Cherubin 1, G. Magnani 1, D. Cattaneo 1, L. Denisov 1, G. Tagliavini 2, G. Agosta 1 and S. Cherubin 3; 1 DEIB, Politecnico di Milano, Milan, Italy; 2 DISI, University of Bologna, Bologna, Italy; 3 IDI, NTNU, Trondheim, Norway., IEEE TRANSACTIONS ON COMPUTERS, VOL. XX, NO. X, AUGUST 202X
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors, Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini, DATE 2025 Conference, https://arxiv.org/abs/2501.10301
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution,Computing Frontiers 2025
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor, Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Computing Frontiers 2025
AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance, Mateo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini, Computing Frontiers 2025
The ISOLDE Space Demonstrator: A Platform for AI Applications on Satellites, Emanuele Valpreda, Roberto Morelli, Antonio Sciarappa, Davide Di Ienno, Carlo Ciancarelli, Paolo Serri, Valeria Parascandolo, antonio leboffe, Dario Pascucci, Daniele Gregori, Mattia Paladino, Daniele Jahier Pagliari, Alessio Burrello, Sara Vinco, Gianvito Urgese, Maurizio Martina, Guido Masera, William Fornaciari, Federico Reghenzani, Andrea Galimberti, Giovanni Agosta, Davide Zoni, Andrea Acquaviva, Francesco Conti, RISC-V in Space Workshop
Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs, Pablo Andreu, Sergi Alcaide, Pedro Lopez, Jaume Abella, Carles Hernández, Future Generation Computer Systems, https://www.sciencedirect.com/science/article/pii/S0167739X24004825
Model Predictive Control Acceleration on RISC-V, Martin Kostal, NXP Semiconductors, Poster, HiPeac 2025
SIMD Extensions – A Historical Perspective, Diana Vuta-Popescu, Ionut, Catalin Antofi, Catalin Bogdan Ciobanu, Csaba Zoltan Kertesz, 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME)
TIE Micro – Chiplets and Next-gen Packaging, Catalin Bogdan Ciobanu, Dan Manolescu, Roxana Vladuta, Luciana Chitu, Cosmin Moisa, Marcel Manofu, Paul Svasta, 2024 IEEE 30th International Symposium for Design and Technology in Electronic Packaging (SIITME)
Systolic Array Matrix Multiplication Accelerator, Alexandru Puscasu, Catalin Bogdan Ciobanu, Octavian Buiu, International Semiconductor Conference (CAS)
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads, Matteo Perotti†, Michele Raeber†, Mattia Sinigaglia*, Matheus Cavalcante†, Davide Rossi*, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), ASAP 2024 Conference, https://arxiv.org/abs/2407.05447
RISC-V Accelerators, Enablement and Applications for Automotive and Smart Home in the ISOLDE Project, Cătălin Bogdan Ciobanu, Honorius Gâlmeanu, Alexandru Puscasu, Mihai Gologanu, Octavian Buiu, Mihai Antonescu, Vlad-Gabriel Serbu, Vasile-Mădălin Moise, Cristian-Tiberius Axinte, Alexandru-Tudor Popovici, George-Iulian Uleru, Andrei Stan, Mihai Munteanu, Alexandru Drîmbărean, Csaba Nemeti, Dănut Rotar, Cosmin Moisa, Bogdan Ditu, Petre Cristian Trusca, Marius Antache, Simona Costinescu, Mari-Anais Sachian, George Suciu, Cristian Gheorghe, Cristina Tudor, Kejsi Koci, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2024 conference
Integration and Optimization of EV Charging Processes in a Decentralized Local Energy Trading Market, Christoph Groß; Tin Stribor Sohn; Oliver Bringmann, 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS), https://www.researchgate.net/publication/383162902_Integration_and_Optim...
Onchip Traffic Injection to Counteract Timing Side-Channel Attacks, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella; †Barcelona Supercomputing Center (BSC) ‡Microelectronic and Electronic Systems Department, Barcelona, Spain Universitat Aut`onoma de Barcelona (UAB), Bellaterra, Spain, Embedded Real Time Systems (ERST) 2024 conference, https://hal.science/hal-04614786
RISC-V on mixed-critical platforms (poster + published extended abstract), Samuel Ardaya-Lieb, Holger Blasum, Enkhtuvshin Janchivnyambuu, Florian Krebs, Jan Reinhard, Darshak Sheladiya and George Violettas, RISC-V Summit Munich 2024, https://www.sysgo.com/fileadmin/user_upload/data/blog/SYSGO_2024-06_Mixe...
Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium, Xavier Carril, Charalampos Kardaris, Jordi Ribes-González, Oriol Farràs, Carles Hernandez, Vatistas Kostalabros, Joel Ulises González-Jiménez, Miquel Moretó, ACM Transactions on Reconfigurable Technology and Systems, https://dl.acm.org/doi/abs/10.1145/3675172
SETHET – Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story, Gabriele Magnani1, Daniele Cattaneo1, Lev Denisov1, Giuseppe Tagliavini2, Giovanni Agosta1, Stefano Cherubin3; 1 Politecnico di Milano (Italy), 2 University of Bologna (Italy), 3 NTNU (Norway), ACM Computing Frontiers 2024
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine, Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomas Gomez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini, IEEE Journal of Solid-State Circuits, https://hdl.handle.net/11585/953203
Accelerating WebAssembly Interpreters in Embedded Systems through Hardware-Assisted Dispatching, Matthias Rupp, Stefan Wallentowitz, ARCS Conference 2024
The European Chips Act, The ISOLDE Project, and Open-Source Hardware, Willibald Krenn; Andrew Wilson; Ambily Suresh; Manuel Freiberger (Silicon Austria Labs, Graz), 2024 Argentine Conference on Electronics (CAE)
MX: Enhancing RISC-V’s Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication, Matteo Perotti†, Yichao Zhang†, Matheus Cavalcante†, Enis Mustafa†, Luca Benini†*, †ETHZ (ETH Zurich, Switzerland), *UNIBO (Universita' di Bologna, Italy), DATE 2024 Conference, https://arxiv.org/pdf/2401.04012.pdf
A Model-Driven Architecture Approach to Efficient and Adaptable Software Code Generation, Mayuri Bhadra, Daniel Albert, Ungsang Yun, Robert Kunzelmann, Daniela Sanchez Loperera and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564525
A Comparative Analysis of ARM and RISC-V ISAs for Deeply Embedded Systems, Natalie Simson, Ares Tahiraga and Wolfgang Ecker, Infineon Technologies AG, Munich, MBMV 2024 Proceedings, https://ieeexplore.ieee.org/document/10564506
Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story, Francisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2023, http://hdl.handle.net/2117/397442
SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core, Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella, IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2023, http://hdl.handle.net/2117/393235
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project, William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario DiCarlo, and Antonio Sciarappa, 1 Politecnico di Milano, Milano, Italy, 2 University of Bologna, Bologna, Italy, 3 E4 Computer Engineering SpA, Italy, 4 Thales Alenia Space Italia S.p.A., Italy, 5 Politecnico di Torino, Torino, Italy, 6 Leonardo SpA, Italy, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) 2023 conference, https://re.public.polimi.it/retrieve/ceb20d00-33d1-41df-8a37-1870b06ea92...
Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains, Jaume Abella, Francisco J. Cazorla, Sergi Alcaide, Michael Paulitsch, Yang Peng, Inês Pinto Gouveia, (white paper), https://arxiv.org/abs/2307.11940
